As a part of designing a circuit, such as an integrated circuit (IC) circuit, an electronic design automation (EDA) software system commonly performs generation of a clock tree, which uses a branching network to distribute a clock signal from a clock signal source to a plurality of clock sinks within a circuit design. The clock sinks usually comprise clock sinks in the circuit design that require a clock signal to operate, such as flip-flops. The branching network forming the circuit is comprised of nodes connected by nets.
One style for clock-tree design is to have a portion of the clock-tree be highly structured. This highly structured portion is given preferential circuit resources so that it may have improved performance, power or yield attributes. Examples of such structured circuits are H-trees, meshes and fishbones. These circuits are designed such that the delay from the source node to a plurality of clock tapping point nodes (hereafter, clock tap) is such that delay is closely matched. Each circuit path from the source to the tap-point is logically equivalent such that any clock tap can be logically used to connect to the remaining clock circuit to a specific sink. The choice of clock tap will impact performance to a sink and thus the performance of the IC.
The remaining portion of each circuit to each clock sink will be comprised of additional nodes. Those nodes may exist solely to meet electrical requirements, or for managing the delay of the circuit to each sink. Such nodes are usually inverters or buffers. Other nodes may have a logical or control function in the path to a sink, a common element is a clock-gate or integrated clock gate (ICG) which is used to turn off the clock sinks and logic paths they contribute to. Under designed specific conditions, a final circuit resulting from the given circuit design can use an ICG to turn off a cluster of clock sinks (e.g., flip-flops) if the cluster is not required for certain operations of the final circuit for the active operation of the IC. In this way, the ICG can permit the final circuit to save power that would otherwise be consumed by the cluster had it not been gated from the clock tap by the ICG. ICGs themselves are power and area expensive. If too many copies of logically equivalent ICGs are made this will negatively impact power.
Multiple sinks may have common ICG and logic conditions. If such sinks are assigned to a plurality of tap-points, the clock gate and logic will have to be replicated for each tap. Once an assignment of a sink to a clock tap is made and necessary ICGs and logic is duplicated, each clock tap will form a plurality of subordinate clock trees. This plurality of subordinate clock trees may be collectively referred to as a source group and shares common clock optimization goals and constraints.
Conventional clock tap assignment is performed before clock tree synthesis of the subordinate clock trees. In a multi-clock source context, conventional clock tap assignment process is based on geometric distance, where each clock sink is assigned to a nearest clock tap using a “nearest neighbor” approach this approach will optimize the performance of the subordinate clock tree. Additionally, conventional clock tap assignment may consider further away taps to reduce ICG count while maintaining reasonable clock tap-to-clock sink path length and clock tap fanout.